Half Price Standard Code

HSUL_12 LPDDR2 I/O
standard by JEDEC Solid State Technology Association, 08/01/2009

MEASURING WHISKER GROWTH ON TIN AND TIN ALLOY SURFACE FINISHES
standard by JEDEC Solid State Technology Association, 07/01/2008

MARKING AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES
standard by JEDEC Solid State Technology Association, 05/01/2007

ADDENDUM No. 2 to JESD35 – TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 02/01/1996

RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT
standard by JEDEC Solid State Technology Association, 12/01/2008

GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS
standard by JEDEC Solid State Technology Association, 09/01/1998

STANDARD MANUFACTURER'S IDENTIFICATION CODE
standard by JEDEC Solid State Technology Association, 01/01/2014

FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)
standard by JEDEC Solid State Technology Association, 07/01/2008

Notification Standard for Product Discontinuance
standard by JEDEC Solid State Technology Association, 11/01/2014

DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007