Half Price Standard Code

ADDENDUM No. 5 to JESD12 – DESIGN FOR TESTABILITY GUIDELINES
Amendment by JEDEC Solid State Technology Association, 08/01/1988

WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 04/01/2017

INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW TROUGH A SINGLE PATH
standard by JEDEC Solid State Technology Association, 11/01/2010

RF Biased Life (RFBL) Test Method
standard by JEDEC Solid State Technology Association, 01/01/2013

Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA)
standard by JEDEC Solid State Technology Association, 01/01/2013

GUIDELINES FOR REPORTING AND USING ELECTRONIC PACKAGE THERMAL INFORMATION
standard by JEDEC Solid State Technology Association, 11/01/2012

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD
standard by JEDEC Solid State Technology Association, 03/01/2016

SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICES
standard by JEDEC Solid State Technology Association,

INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES
standard by JEDEC Solid State Technology Association, 11/01/2017

POD135 – 1.35 V Pseudo Open Drain I/O
standard by JEDEC Solid State Technology Association, 06/01/2019