Half Price Standard Code

THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2008

I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD
standard by JEDEC Solid State Technology Association, 02/01/1999

STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 02/01/1996

GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2002

POD125 – 1.25 V PSEUDO OPEN DRAIN I/O
standard by JEDEC Solid State Technology Association, 09/01/2017

ADDENDUM No. 10 to JESD24 – TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES
Amendment by JEDEC Solid State Technology Association, 08/01/1994

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 02/01/2011

GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING
standard by JEDEC Solid State Technology Association, 12/01/2000

Universal Flash Storage (UFS) Test
standard by JEDEC Solid State Technology Association, 07/01/2017

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS
standard by JEDEC Solid State Technology Association, 08/01/2003